31. Editing Verilog and SystemVerilog HDL Source

This mode is used to edit Verilog and SystemVerilog source files. It is automatically invoked for buffers visiting any file ending with one of the following extensions: `.vh?', `.svh?', `.dv'.

The mode provides the following features:

• NEWLINE, TAB indents for Verilog code.
• Delete converts tabs to spaces as it moves back.
• Supports highlighting.
• Supports SystemVerilog OVM (Open Verification Methodology) macros.

This documentation is only a teaser and does not claim to be complete. Please check out http://www.veripool.org/wiki/verilog-mode/Documentation for further information, FAQ and change history.

The variables controlling indentation/edit style are:

verilog-indent-level

Indentation of Verilog statements with respect to containing block.

verilog-indent-level-module

Absolute indentation of Module level Verilog statements. Set to 0 to get initial and always statements lined up on the left side of your screen.

verilog-indent-level-declaration

Indentation of declarations with respect to containing block. Set to 0 to get them list right under containing block.

verilog-indent-level-behavioral

Indentation of first begin in a task or function block Set to 0 to get such code to lined up underneath the task or function keyword

verilog-indent-level-directive

Indentation of `ifdef/`endif blocks

`verilog-cexp-indent

Indentation of Verilog statements broken across lines i.e.:

if (a) begin

verilog-case-indent

Indentation for case statements.

verilog-auto-newline

Non-nil means automatically newline after semicolons and the punctuation mark after an end.

verilog-auto-indent-on-newline

Non-nil means automatically indent line after newline

verilog-tab-always-indent

Non-nil means TAB in Verilog mode should always reindent the current line, regardless of where in the line point is when the TAB command is used.

verilog-indent-begin-after-if

Non-nil means to indent begin statements following a preceding if, else, while, for and repeat statements, if any. otherwise, the begin is lined up with the preceding token. If t, you get:

if (a) begin // amount of indent based on `verilog-cexp-indent'

otherwise you get:

if (a) begin

verilog-auto-endcomments

Non-nil means a comment /* ... */ is set after the ends which ends cases, tasks, functions and modules. The type and name of the object will be set between the braces.

verilog-minimum-comment-distance

Minimum distance (in lines) between begin and end required before a comment will be inserted. Setting this variable to zero results in every end acquiring a comment; the default avoids too many redundant comments in tight quarters.

verilog-auto-lineup

List of contexts where auto lineup of :'s or ='s should be done.

Turning on Verilog mode calls the value of the variable verilog-mode-hook with no args, if that value is non-nil.

Other useful functions are:

verilog-complete-word

complete word with appropriate possibilities (functions, verilog keywords...)

verilog-comment-region

Put marked area in a comment, fixing nested comments.

verilog-uncomment-region

Uncomment an area commented with verilog-comment-region.

verilog-insert-block

insert begin ... end;

verilog-star-comment

insert /* ... */

verilog-mark-defun

Mark function.

verilog-beg-of-defun

Move to beginning of current function.

verilog-end-of-defun

Move to end of current function.

verilog-label-be

Label matching begin ... end, fork ... join and case ... endcase statements

verilog-sk-always

Insert a always @(AS) begin .. end block

verilog-sk-begin

Insert a begin .. end block

verilog-sk-case

Insert a case block, prompting for details

verilog-sk-else

Insert an else begin .. end block

verilog-sk-for

Insert a for (...) begin .. end block, prompting for details

verilog-sk-generate

Insert a generate .. endgenerate block

verilog-sk-header

Insert a nice header block at the top of file

verilog-sk-initial

Insert an initial begin .. end block

verilog-sk-fork

Insert a fork begin .. end .. join block

verilog-sk-module

Insert a module .. (/*AUTOARG*/);.. endmodule block

verilog-sk-primitive

Insert a primitive .. (.. );.. endprimitive block

verilog-sk-repeat

Insert a repeat (..) begin .. end block

verilog-sk-specify

Insert a specify .. endspecify block

verilog-sk-task

Insert a task .. begin .. end endtask block

verilog-sk-while

Insert a while (...) begin .. end block, prompting for details

verilog-sk-casex

Insert a casex (...) item: begin.. end endcase block, prompting for details

verilog-sk-casez

Insert a casez (...) item: begin.. end endcase block, prompting for details

verilog-sk-if

Insert an if (..) begin .. end block

verilog-sk-else-if

Insert an else if (..) begin .. end block

verilog-sk-comment

Insert a comment block

verilog-sk-assign

Insert an assign .. = ..; statement

verilog-sk-function

Insert a function .. begin .. end endfunction block

verilog-sk-input

Insert an input declaration, prompting for details

verilog-sk-output

Insert an output declaration, prompting for details

verilog-sk-state-machine

Insert a state machine definition, prompting for details!

verilog-sk-inout

Insert an inout declaration, prompting for details

verilog-sk-wire

Insert a wire declaration, prompting for details

verilog-sk-reg

Insert a register declaration, prompting for details"

To configure this package, type:

  M-x customize-group RET verilog-mode RET

31.1 About Verilog

Verilog (IEEE 1364) and SystemVerilog (IEEE 1800) HDL are hardware description languages used to design and document electronic systems. In December 2007 IEEE 1364 has been merged into IEEE 1800, paving the way for SystemVerilog as the official successor to Verilog.

SystemVerilog HDL allows designers to design at various levels of abstraction.

For more information, see http://www.systemverilog.org/.

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